1. Field of the Invention
The present invention relates to a semiconductor storage device such as an electrically erasable programmable read only memory (EEPROM) and in particular, to a semiconductor storage device made from an all-at-once erasable flush memory.
2. Description of Related Art
Currently, various memory devices are uses in various electronic apparatuses. Among such memory devices, there are those which retain a binary data in a rewritable and nonvolatile manner.
The flash memory can be divided into several groups according to an internal structure and a writing method. For example, there are NAND type and NOR type. The NOR type may be AND type or DINOR (divided bit line NOR) type. The DONOR type is considered to be advantageous because of its high speed operation while the AND type is considered to be advantageous for high integration.
Here, explanation will be given on a conventional example of such a semiconductor storage device with reference to FIG. 4 to FIG. 10. It should be noted that FIG. 4 is a plan view schematically showing an entire configuration of a flash memory as the semiconductor storage device; FIG. 5 is a plan view schematically showing a layered configuration of memory cells; FIG. 6 is a schematic front view showing a cross section about Xxe2x80x94X in FIG. 5; FIG. 7 is a schematic side view showing a cross section about Yxe2x80x94Y in FIG. 5; FIG. 8 schematically shows a state for writing a data in a memory cell; FIG. 9 schematically shows a state for erasing a data in a memory cell by the substrate erase method; and FIG. 10 shows a cell threshold value characteristic to memory cells.
Here, a flash memory 100 as a conventional example of the semiconductor storage device. includes numerous memory cells 101 which are arranged on the surface of a semiconductor substrate 102 in a two-dimensional structure. As shown in FIG. 4, the memory cells 101 are grouped into a plurality of sectors 103.
Each memory cell 101 consists of at least one MOS transistor having, as shown in FIG. 5 to FIG. 7, a source region 111, a drain region 112, a floating gate (FG) 113, a control gate (CG) 114, insulation films 115, 116 and the like. Each of the regions 111 and 112 is a diffused layer formed on the semiconductor substrate 102. The FG 113 is located on a diffused layer 117 between the regions 111 and 112.
As has been described above, a plurality of sectors 103 are arranged in the two-dimensional manner on a semiconductor substrate 102 of the flash memory 100, and on each of the sectors 103, there are arranged a plurality of memory cells 101. These memory cells 101 are separated from one another by an element isolation region 118 of LOCOS (local oxidization of silicon) and STI (shallow trench isolation).
It should be noted that in the intermediate region between adjacent sectors 103, various circuits are arranged including a line decoder, a column decoder, a column selection circuit, a sense amplifier, and the like. For example, the plurality of sectors 103 are arranged in the column direction via a space of xe2x80x9c510 (xcexcm)xe2x80x9d, where the column selection. circuit (Y selector) is arranged.
Moreover, the plurality of sectors 103 are arranged in the line. direction via a space of xe2x80x9c330 (xcexcm)xe2x80x9d, where the line decoder (X decoder) is arranged. It should be noted that the space in the line direction of the plurality of sectors 103 where no such circuit is arranged is formed with a width of, for example, xe2x80x9c65 (xcexcm)xe2x80x9d.
In the flash memory 100 having the aforementioned configuration, a binary data can be written in each of the memory cells 101. When writing a new data or rewriting a data stored in the flash memory 100, the stored data in memory cells 101 are erased on the sector 103 basis immediately before the writing.
When writing a binary data in a memory cell 101, as shown in FIG. 8, a predetermined potential is applied to the source region 111, the drain region 112, and the CG 114 and electric charge (electrons) is poured from the semiconductor substrate 102 into the FG 113.
Here, in the memory cell 101 where a data is to be written, for example, xe2x80x9c0 (V)xe2x80x9d is applied to the source region 111, xe2x80x9c5 (V)xe2x80x9d is applied to the drain region, and xe2x80x9c10 (V)xe2x80x9d is applied to the CG 114. Accordingly, an electric charge is poured into the FG 113 and the cell threshold value becomes above a write reference. Simultaneously with this, in a memory cell 101 where no data is to be written, for example, xe2x80x9c0 (V)xe2x80x9d is applied to the drain region 112 (not depicted) and not electric charge is poured into the FG 113, thereby the cell threshold value is retained below the erase reference.
As shown in FIG. 10, the cell threshold value of the memory cell 101 becomes above the write reference or the below the erase reference. Thus, by detecting this, it is possible to read a binary data which has been written or erased.
When performing such a data read, for example, xe2x80x9c0 (V)xe2x80x9d is applied to the source region 111, xe2x80x9c1 (V)xe2x80x9d is applied to the drain region, and xe2x80x9c3 (V)xe2x80x9d is applied to the CG 114, so that the current flowing through the drain region 112 is detected by the sense amplifier (not depicted) to determine the stored data to be 1 or 0.
On the other hand, when erasing data stored in all the memory cells 101 of a certain sector 103, for example, xe2x80x9cxe2x88x9210 (V)xe2x80x9d is applied to the CG 114, xe2x80x9c+10 (V)xe2x80x9d is applied to the diffused layer 117, and the source region 111 and the drain region 112 are made into an open state, so that as shown in FIG. 9, electric charge (electrons) is discharged from the FG 113 to the diffused layer 117. As shown in FIG. 10, thus, the cell threshold value of the memory cell 101 becomes below the erase reference and in this memory cell 101, the stored data has been erased.
It should be noted that the aforementioned data erase in the memory cell 101 is performed for each of the sectors 103. Accordingly, until the cell threshold values of all the memory cells 101 in that sector 103 become below the erase reference, data erase is uniformly performed in all the memory cells 101 of the sector 103.
However, because of the production errors, the erase speed is not completely identical in all the memory cells 101. Accordingly, if the data erase is uniformly performed in all the memory cells 101 one sector, the data erase may be performed excessively in a memory cell 101 having a high erase speed.
In that memory cell 101, the cell threshold value is significantly lowered. However, if a particular memory cell 101 in the flash memory 100 has a too low cell threshold value, there arise a problem of read failure. For example, in an ordinary NOR type cell array, drain regions 112 of a plurality of memory cells 101 are connected to a single bit line. When a predetermined voltage such as xe2x80x9c3 (V)xe2x80x9d is applied to one of the word lines (CG 114) of the plurality of the memory cells 101, the memory cell 101 connected to that word line is selected and the stored data is read out.
Here, if the selected memory cell 101 contains a written data, no detection current is generated and the stored data is determined to be xe2x80x9c1xe2x80x9d by the sense amplifier, and if the selected memory cell 101 contains no written data, a read current is generated and the stored data is determined to be xe2x80x9c0xe2x80x9d.
However, in a memory cell 101 where a data erase has been performed excessively, a read current may be generated even when the predetermined voltage is not applied to the word line (CF 114). That is, even when the memory cell 101 has a written data, the stored data may be determined to be xe2x80x9c0xe2x80x9d, causing a read failure.
In order to cope with this, in the current flash memory, as shown in FIG. 10, when a data erase is performed in a certain sector 103, electric charge is given to those memory cells 101 having the cell threshold values of the FG 113 below a predetermined lower limit value.
This is called a write-back processing or the like. While an ordinary data erase is performed for the respective sectors 103 or for the entire memory, the write-back processing is performed by detecting respective memory cells having an excessive erase. Here, an excessive erase verify is executed and if the cell threshold value is still below the lower limit, the write-back processing is again executed.
It should be noted that the above explanation has been given on the substrate erase method as the data erase method of the flash memory 100. The data erase method may also be the source erase method. In the source erase method, when erasing written data in all the memory cells 101 of a certain sector 103, as shown in FIG. 14, xe2x80x9cxe2x88x9210 (V)xe2x80x9d is applied to the CG 114, xe2x80x9c+10 (V)xe2x80x9d is applied to the source region, xe2x80x9c0 (V)xe2x80x9d is applied to the diffused layer, and the drain region 112 is in the open state. Thus, electrons are discharged from the FG 113 to the source region 111 and the written data in the memory cells 101 is erased.
In the aforementioned flash memory 100, a binary data can be written into memory cells 1001 by making the cell threshold value of the FG 113 above the write reference and the stored data in the memory cells 101 can be erased by making the cell threshold value of the FG 113 below the erase reference. The data erase is performed uniformly in the numerous memory cells of a single sector 103. Those memory cells 101 having the cell threshold values below the lower limit are supplied with electric charge and no problem such as leak current is caused.
However, this electric charge supply requires a time, increasing the erase time of the sector 103. Accordingly, the number of memory cells 101 requiring electric charge supply is preferably as small as possible. If the erase speeds of all the memory cells 101 in a sector 103 are completely identical, no excessive data erase is caused and no electric charge supply is required, thereby reducing the erase time of the sector 103.
In an actual memory cell 101, each part consists of a diffused region and a layered film. As the portions associated with the erase speed, as shown in FIG. 5 and FIG. 7, there are a diffused layer width W, an overlap B of the FG 113 with respect to the element isolation region 118, and the like. It should be noted that the diffused layer width W, as shown in FIG. 5 and FIG. 7, is a dimension in a horizontal direction in the figures equivalent to the entire length of the diffused layer between the element isolation regions 118.
When a memory cell 101 of the flash memory 100 of the substrate erase method is expressed in a capacitance equivalent circuit, as shown in FIG. 11, a capacitance Cl between the FG 113 and the diffused layer 117, a capacitance C2 between the FD 113 and the CG 114, a potential difference VFG between the FG 113 and the diffused layer 117, and a potential difference VCG between the FG 113 and the CG 114 satisfy a relationship as follows:
VFG=(C2/C1)xc3x97VCG
For example, when the capacitance C2 between the FG 113 and the CG 114 is constant, if the aforementioned diffused layer width W increases, the capacitance C1 also increases. Accordingly, the potential difference VFG is lowered to lower the erase speed. Moreover, if the diffused layer width W is constant and the overlap B is reduced, the capacitance C2 is also lowered, thereby reducing the potential difference VFG to lower the erase speed.
On the other hand, when a memory cell 101 of a flash memory 100 of the source erase method is expressed in a capacitance equivalent circuit, as shown in FIG. 15, a capacitance C1 between the FG and the diffused layer 117, a capacitance C2 between the FG 113 and the CG 114, a capacitance Ce between the FG 113 and the source region 111, a potential difference VS between the CG 114 and the source region 111, and a potential difference VSG. between the FG 113 and the source region 111 satisfy a relationship as follows:
VSG=(C1+C2)/(C1+C2+Ce)xc3x97VS
Accordingly, in the flash memory 100 of the source erase method, if the diffused layer width W is increased, the capacitance C1 and the potential difference VSG are increased, thereby lowering the erase speed, and if the overlap B is reduced, the capacitance C2 and the potential difference VSG are lowered, thereby increasing the erase speed.
Accordingly, in either of the erase methods of the flash memory 100, if the diffused layer width W and the overlap B in all the memory cells 101 of one sector 103 are identical, the erase speeds are also identical. However, when the flash memory 100 was actually produced, it was found that the diffused layer width W and the overlap B in a sector cannot be made identical due to the production technique and the production condition.
For example, when a flash memory 100 of the substrate erase method is produced, as shown in FIG. 12, the diffused layer width W may be greater in a central region than in end regions of the sector 103. If data erase is performed in a sector 103 of a substrate erase type flash memory having such a configuration, the erase speed is lowered in the memory cells 101 in the end regions.
However, the data erase is performed until the cell threshold values of all the memory cells 101 in the sector 103 become below the erase reference. Accordingly, as shown in FIG. 13, when the data erase is at a low speed only in some memory cells .101, the data erase is performed in the most of the memory cells 101 more than necessary.
For this, when a data erase is performed in a sector 103, most of the memory cells 101 in the center region often have cell threshold values below the lower limit and a plenty of memory cells 101 require write-back, which results in increase of the erase time of the sector 103.
On the contrary, when a flash memory of the source erase type is produced, the diffused layer width W may become smaller in the end regions of the sector 103 than in the center region. However, in this case also, a plenty of memory cells 101 require a write-back processing in the sector 103 where the data erase is performed and the erase time is increased.
It should be noted that in order to prevent the aforementioned production irregularities, there is a technique to produce a dummy pattern similar to the memory cell 101 up to the outer side of the sector 103. However, this is not preferable because this lowers the productivity of the flash memory 100 and increases the apparatus size.
It is therefore an object of the present invention to provide a semiconductor storage device capable of uniform data erase in a group of memory cells with a reduced number of cells in which the data erase is excessively performed and completing the data erase at a high speed, and a production method thereof.
The semiconductor storage device according to the invention comprises a group of memory cells arranged in a two-dimensional state on a semiconductor substrate, wherein a binary data write is performed by pouring electric charge into each of the memory cells of the group until a cell threshold value reaches a predetermined write reference while a binary data erase is performed by uniformly discharging the electric charge from the memory cells until all the cell threshold values become below a predetermined erase reference and those memory cells subjected to the data erase and having cell threshold values below a lower limit are supplied with an electric charge,
the device being characterized in that when a production error occurs in such a way that an erase speed of memory cells in a predetermined position of the group differs from an ideal value,
the device is formed with such a configuration that in the memory cells in the predetermined position, the erase speed is higher than an ideal value even if the production error occurs.
Accordingly, in the semiconductor storage device of the present invention, a data write is performed to each of the memory cells while a data erase is uniformly performed to all the memory cells of a predetermined group. When a production error occurs to lower an erase speed of some memory cells at a predetermine position of the group than an ideal value, the data erase is uniformly performed in all the memory cells of the group until the data erase is complete in the memory cells subjected to the production error. Consequently the data erase is performed more than necessary in most of the memory cells of the group and a plenty of memory cells require electric charge supply.
However, the semiconductor storage device according to the present invention is formed with a such a configuration that memory cells at a position where the production error occurs have a higher erase speed than an ideal value even if the production error occurs and accordingly, the memory cells thus formed will not lower their erase speed than the ideal value even if the production error occurs. These memory cells thus formed have a higher erase speed than most of the memory cells of the group, the data erase may be performed more than necessary requiring electric charge supply.
However, in most of the memory cells other than the aforementioned, the data erase will not performed more than necessary and it is possible to reduce the number of memory cells in which the data erase is performed excessively requiring electric charge supply. It should be noted that xe2x80x9csome memory cellsxe2x80x9d of a group means less than half of the group, for example, one tenth of the memory cells of the group.